Preview Learn Verilog HDL Coding: From Basics to ASIC Flow

Reference Materials

SP Verilog Book

Tools & Installation

Lec-1 : Xilinx Vivado Installation

Lec-2 : Xilinx Vivado Installation

Lec-3 : Xilinx Vivado Installation

Lec-4 : Xilinx Vivado Installation

Lec-5 : Getting Started with EDA Playground

Course Contents

Module-1 Introduction to Verilog HDL

Module-2 Verilog Syntax and Coding Guidelines

Module-3 Data Types I

Module-4 Data Types II

Module-5 Operators in Verilog HDL

Module-6 Blocking & Non Blocking Assignments

Module-7 Synchronous Circuit & Asynchronous Circuit

Module-8 Delays in Procedural Assignment

Module -9 Block Statements

Module-10 Timing Control Statement

Module -11 Branching Constructs & Loops-

Module-12 Functions & Tasks

Module-13 System Task in Verilog

Module-14 Compiler Directives in Verilog

Module-15 FSM using Verilog HDL

Verilog Labs

Lab-1 : Write Design & TB code for Half Adder

Lab-2 : Write RTL & TB Code for Full Adder

Lab-3 : Write RTL & TB Code for Arithmetic Design Unit (ALU)

Lab-4 : Write RTL & TB Code for 4x1 Multiplexer

Lab-5 : Write RTL & TB Code for 3x8 Decorder

Lab-6 : Write RTL & TB Code for 8x3 Priority Encorder

Lab-7 : Write RTL & TB Code for DFF, TFF and JK Flip Flop

Lab-8 : Write RTL & TB Code for Serial -In-Serial-Out 4 Bit.

Lab-9 : Write RTL & TB Code for Sequence Detector 101 Melay Type Overlapping

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